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esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 1/14 1.5mhz 3a, synchronous step-down regulator general description EML3170 is a high efficiency current mode synchronous buck pwm dc-dc regulator. the internal generated 0.8v precision feedback reference voltage is designed for low output voltag e. low r ds (on) synchronous switch dramatically reduces conduction loss. to extend battery life for portabl e application, 100% duty cycle is supported for low-dropout operation. shutdown mode also helps saving the current consumption. features input voltage range: 2.5 to 5.5v adjustable output voltage from 0.8v to v in precision feedback reference voltage: 0.8v (2%) output current: 3a (max.) duty cycle: 0~100% internal fixed pwm frequency: 1.5mhz low quiescent current: 100 a no schottky diode required built-in soft start current mode operation over temperature protection applications cellular telephone wireless and dsl modems digital still cameras portable products mp3 players typical application ) 1( 2 1 r r v v fb out + =
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 2/14 package configuration e-sop-8l EML3170-00se08nrr 00 adjustable se08 e-sop-8l package nrr rohs & halogen free package commercial grade temperature rating: -40 to 85c package in tape & reel order, mark & packing information package vout(v) product id marking packing e-sop-8l adjustable EML3170-00se08nrr tape & reel 3k units functional block diagram
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 3/14 pin functions pin name e-sop-8l function vcc 1 power input pin. must be closely decoupled to gnd pin with a 10 f or greater ceramic capacitor. nc 2 nc. gnd 3 ground pin. fb 4 feedback pin. receives the feedback voltage from an external resi stive divider across the output. en 5 enable pin. minimum 1.5v to enable the device. maximum 0.3v to shut down the device. pgnd 6 power switch ground pin. sw 7 switch pin. must be connected to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches . vin 8 input supply pin. must be closely decoupled to gnd pin with a 10 f or greater ceramic capacitor. exposed pad 9 thermal pad. connect to gnd.
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 4/14 absolute maximum ratings devices are subjected to fail if they stay above ab solute maximum ratings. input voltage (vin, vcc) ----------------------- ? 0.3v to 6v en, fb voltages ----------------------------------- --- ? 0.3v to v in sw voltage ------------------------------- ? 0.3v t o (v in + 0.3v) sw pin switch current (dc) ------------------------ -------- 3.9a sw pin switch current (ac) ------------------------ ---------- 6a lead temperature (soldering, 10 sec)--------------- - 260c operating temperature range ---------- ?40c to 85 c junction temperature (note 1) --------------------- --- 150c storage temperature range ------------- ? 65c to 1 50c esd susceptibility hbm ---------------------------- ----------- 2kv mm ------------------------------ ------- 200v thermal data package thermal resistance parameter value ja (note 2) junction-ambient 50 o c/w e-sop-8l jc (note 3) junction-case 10 o c/w electrical characteristics v in =v vcc =v en =3.6v, v out =1.2v, v fb =0.8v, l=2.2uh, c in =10uf, c out =22uf, t a = 25c. symbol parameter conditions min typ max units v in input voltage range 2.5 5.5 v v fb regulated feedback voltage 0.784 0.800 0.816 v v out % output voltage accuracy i out =10ma to 3.0a -3 +3 % i lsw sw leakage v en =0v, v in =5v 0.01 1 a shutdown , v en = 0v 0.1 1 a active, v fb =0.7v, v en =v in 100 a iq quiescent current pfm, v fb =0.9v, v en =v in 80 a i ocp over current limit v fb =0.7v 3.75 5 6 a f osc oscillator frequency vfb=0.8v, -40 ~+85 1.2 1.5 1.8 mhz r on(p) r ds(on) of pmos i out =100ma 60 90 m r on(n) r ds(on) of nmos i out =100ma 60 90 m v en enable threshold -40 ~+85 0.3 1 1.5 v i en en leakage current -40 ~+85 0.01 1 a ? v fb line regulation with v ref v in =2.5v to 5.5v 0.04 0.4 % / v ? v out output voltage lineregulation v in =2.5v to 5.5v 0.04 0.4 % / v note 1: t j is a function of the ambient temperature t a and power dissipation p d (t j = t a + (p d ) * ja )). note 2: ja is measured in the natural convection at t a =25 on a highly effective thermal conductivity test bo ard (2 layers , 2s0p ) according to the jedec 5 1-7 thermal measurement standard. note 3: jc represents the heat resistance between the chip an d the package top case.
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 5/14 typical performance characteristics v in =3.3v, t a =2 5 55 5 , unless otherwise specified shutdown current vs. input voltage line regulation shutdown current vs. input voltage 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) s h u td o w n c u rre n t (u a ) ven=0 v line regulation 0.59 0.592 0.594 0.596 0.598 0.6 0.602 0.604 0.606 0.608 0.61 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) r e fe re n c e v o lta g e (v ) vin=3.3v vout=1.8v load regulation frequency vs. input voltage load regulation 1.7 1.71 1.72 1.73 1.74 1.75 1.76 1.77 1.78 1.79 1.8 0.5 1 1.5 2 2.5 3 output current (a) o u tp u t v o lt a g e ( v ) vin=3.3v vout=1.8v frequency vs. input voltage 1.45 1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61 1.63 1.65 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) f re q u e n c y (m h z ) vin=3.3v vout=1.8v frequency vs. temperature short circuit frequency vs. temperature 1.45 1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61 1.63 1.65 -40 -20 0 20 40 60 80 100 temperature () f re q u e n c y (m h z ) vin=3.3v vout=1.8v
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 6/14 typical performance characteristics v in =3.3v, t a =2 5 55 5 , unless otherwise specified load transient response enable on i load : 300ma~3a i load : 3a output ripple voltage power on i load : 3 a i load : 3a efficiency (vin=5v) efficiency (vout=1.8v) 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 10000 iout (ma) e ff icien cy ( % ) vout=3.3v vout=1.8v vout=1.2v 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 10000 iout (ma) e f f icien cy ( % ) vin=2.7v vin=3.6v vin=4.2v
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 7/14 function description control loop the EML3170 is a high efficiency current mode synch ronous buck regulator. both the main (p-channel mo sfet) and synchronous (n-channel mosfet) switches are built i nternally. with current mode operation, the pwm du ty is controlled both by the error amplifier output and t he peak inductor current. at the beginning of each cycle, the oscillator turn on the p-mosfet switch to source cu rrent from v in to sw output. then, the chip starts to compare th e inductor current with the error amplifier output. once the inductor current is larger than the error amplifier output, the p-mosfet switch is turned off. when the load cu rrent increases, the feedback voltage fb will drop slightly. this causes the error amplifier to output a higher curre nt level until the prior mentioned peak inductor cu rrent reach the same level. the output voltage then can be sustain ed at the same. when the top p-mosfet switch is off, the bottom syn chronous n-mosfet switch is turned on. once the ind uctor current reverses, both top and bottom mosfet will be turn o ff to leave the sw pin into high impedance state. the EML3170?s current mode control loop also includ es slope compensation to suppress sub-harmonic osci llations at high duty cycles. this slope compensation is achie ved by adding a compensation ramp to the inductor c urrent signal. ldo mode the EML3170?s maximum duty cycle can reach 100%. t hat means the driver?s main switch is turn on throu gh out whole clock cycle. once the duty reaches 100%, the feedback path no longer controls the output voltag e. the output voltage will be the input voltage minus the main switch voltage drop. over current protection EML3170 limits the peak main switch current cycle b y cycle. when over current occurs, chip will turn off the main switch and turn the synchronous switch on until nex t cycle. short circuit protection when the fb pin is drop below 300mv, the chip will tri-state the output pin sw automatically. after 30 0us rest to avoid over heating, chip will re-initiate pwm operation w ith soft start. thermal protection EML3170 will shutdown automatically when the intern al junction temperature reaches 150 to protect both the part and the system.
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 8/14 application information input capacitor selection the input capacitor must be connected to the vin pi n and gnd pin of EML3170 to maintain steady input v oltage and filter out the pulsing input current. the voltage r ating of input capacitor must be greater than maxim um input voltage plus ripple voltage. in switch mode, the input current is discontinuous in a buck converter. the source current waveform of the high-side mosfet is a square wave. to prevent large voltage t ransients, a low esr input capacitor sized for the maximum rms current must be used. the rms value of input capaci tor current can be calculated by: ? ?? ? ? ?? ? ? = in o in o max _ o rms v v 1 v v i i it can be seen that when v o is half of v in , c in is under the worst current stress. the worst curren t stress on c in is i o_max /2. inductor selection the value of the inductor is selected based on the desired ripple current. large inductance gives low inductor ripple current and small inductance result in high ripple current. however, the larger value inductor has a l arger physical size, higher series resistance, and/or lower saturation c urrent. in experience, the value is to allow the pe ak-to-peak ripple current in the inductor to be 10%~20% maximum load current. the inductance value can be calculated by: [ ] in o o o in in o l o in v v i %) 20 ~ % 10( 2 f ) v v ( v v i f ) v v ( l ? = ? ? = the inductor ripple current can be calculated by: ?? ? ?? ? ? = ? in o o l v v 1 l f v i choose an inductor that does not saturate under the worst-case load conditions, which is the load curr ent plus half the peak-to-peak inductor ripple current, even at t he highest operating temperature. the peak inductor current is: 2 i i i l o _ l peak ? + = the inductors in different shape and style are avai lable from manufacturers. shielded inductors are sm all and radiate less emi issue. but they cost more than unshielded inductors. the choice depends on emi requirement, p rice and size. inductor value ( ? h) dimensions (mm) component supplier model 1.0 8.38.34.5 feng-jui tprh8d43-2r2m 1.0 10.310.34.0 feng-jui tprh10d40-2r2m 2.2 8.38.34.5 feng-jui tprh8d43-3r3m 2.2 10.310.34.0 feng-jui tprh10d40-3r3m
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 9/14 output capacitor selection the output capacitor is required to maintain the dc output voltage. low esr capacitors are preferred t o keep the output voltage ripple low. in a buck converter circ uit, output ripple voltage is determined by inducto r value, switching frequency, output capacitor value and esr. the outp ut ripple is determined by: ? ?? ? ? ?? ? + ? = ? out cout l o c f 8 1 esr i v where f = operating frequency, cout= output capacit ance and ? il = ripple current in the inductor. for a fixed ou tput voltage, the output ripple is highest at maximum in put voltage since ? il increases with input voltage. capacitor value case size component supplier model 10 f 0805 taiyo yuden jmk212bj106mg 10 f 0805 tdk c12012x5roj106k 22 f 0805 1206 tdk c2012jb0j226m using ceramic input and output capacitors care must be taken when ceramic capacitors are used at the input and the output. when a ceramic capaci tor is used at the input and the power is supplied by a wa ll adapter through long wires, a load step at the o utput can induce ringing at the input, vin. at best, this rin ging can couple to the output and be mistaken as lo op instability. at worst, a sudden inrush current through the long wir es can potentially cause a voltage spike at v in , which may large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7 r specification. their dielectrics have the best temp erature and voltage characteristics of all the cera mics for a given value and size. output voltage programming in the adjustable version, the output voltage is se t using a resistive voltage divider from the output voltage to fb. the output voltage is: ? ?? ? ? ?? ? + = 2 1 1 8.0 r r v v o
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 10/14 applications pcb layout considerations 10uf c2 10uf c1 2.2uh l1 100k r2 50k r1 1 1 2 2 3 3 j1 jumper 3p 10pf c3 vin vin sc fvin sc svin sc fvout sc svout 22uf c4 22uf c5 sc fgnd sc sgnd sc fb sc lx lx lx vcc 1 nc 2 gnd 3 fb 4 vin 8 lx 7 pgnd 6 en 5 u1 EML3170 1. the power traces, consisting of the gnd, sw and v in trace should be kept short, direct and wide. 2. place c in near v in pin as closely as possible to maintain input volta ge steady and filter out the pulsing input current. 3. the resistive divider r 1 and r 2 must be connected to fb pin directly and as closel y as possible. 4. fb is a sensitive node. please keep it away from sw itching node, sw. a good approach is to route the feedback trace on another pcb layer and have a ground plane between the top and feedback trace routing layer. t his reduces emi radiation on to the dc-dc converter its own voltage feedback trace. 5. keep the gnd plates of c in and c out as close as possible. then connect this to the ground plane (if one is used) with several vias. th is reduces ground plane noise by preventing the switching currents from circulating through the ground plane. it also reduces ground bounce at EML3170 by giving it a low impedance ground connection.
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 11/14 typical schematic for pcb layout (cont.) top layer bottom layer
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 12/14 package information e-sop-8l common dimensions millimeter dimensions inch symbol min. nom. max. min. nom. max. a 1.35 - 1.75 0.053 - 0.069 a1 0.05 0.15 0.002 - 0.006 a2 - - 1.50 - - 0.059 b 0.4 bsc 0.016 bsc d 4.8 - 5.0 0.189 - 0.196 d1 2.0 ref 0.081 ref e 3.8 - 4.0 0.150 - 0.157 e1 2.0 ref 0.081 ref e 1.27 bsc 0.05 bsc h 5.8 - 6.2 0.228 - 0.244 l 0.4 - 1.27 0.016 - 0.050 0 - 8 0 - 8
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 13/14 revision history revision date description 0.1 2012.02.07 original.
esmt/emp preliminary EML3170 elite semiconductor memory technology inc./elite mi cropower inc. publication date : feb. 2012 revision : 0.1 14/14 important notice all rights reserved. no part of this document may be reproduced or dupli cated in any form or by any means without the prior permission of esmt. th e contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibi lity for any error in this document, and reserves the right to change the prod ucts or specification in this document without notice. th e information contained herein is presented only as a guide or examples for the application of our products. no responsibil ity is assumed by esmt for any infringement of patents, copyrights, or other i ntellectual property rights of third parties which may result from its use. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inherently a cer tain rate of failure. to minimize r isks associated with customer's application, adequa te design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making appl ication designs. esmt's products are not authorized for use in crit ical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of appl ication, purchaser must do its own quality assuranc e testing appropriate to such applications.

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